A semiconductor company’s design-in often hinges on whether an engineer can get a working symbol and footprint for their CAD tool. The libraries that supply them increasingly belong to EDA vendors.
Customers design in many tools. Chipmakers need validated, native ECAD models in every one of them, from a source that serves the chipmaker’s interests.
This article covers who owns the CAD model layer today, why coverage breaks across tools, and what a vendor-neutral design-in layer delivers.
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Many semiconductor companies link to third-party libraries for symbols, footprints and 3D models in each EDA format. Since 2019, two major component-model libraries have become part of EDA vendors’ portfolios, and consolidation now extends across PCB design, simulation and product lifecycle management.
| Library or platform | Owner today | How it got there |
|---|---|---|
| Component data, libraries and discovery | ||
| SamacSys (CAD models on many chipmaker and distributor sites) | Siemens, through Supplyframe | Supplyframe announced its acquisition of SamacSys in August 2019; Siemens agreed in May 2021 to acquire Supplyframe for $700 million and completed the deal that year (EE Times; Siemens) |
| Ultra Librarian (vendor-neutral BXL models, 400,000+ registered users reported May 2026) | Cadence, through EMA Design Automation | EMA announced its acquisition of Ultra Librarian’s developer, Accelerated Designs, in August 2016; Cadence announced its acquisition of EMA Design Automation and FlowCAD in May 2026 (EE Times; Cadence) |
| Octopart and Ciiva (electronic-parts search and component management) | Renesas, through Altium | Altium agreed to acquire Octopart and completed its Ciiva acquisition in August 2015; Renesas completed its acquisition of Altium on August 1, 2024 (Altium; Renesas) |
| Engineering content and community | ||
| Wevolver (engineering content platform reaching millions of engineers monthly) | Siemens, through Supplyframe | Siemens announced its intention to acquire Wevolver on April 30, 2025, adding it to the Supplyframe network; terms not disclosed (Siemens; Supplyframe) |
| Electronic and PCB design | ||
| Altium (PCB design software, Altium 365 cloud platform and Upverter) | Renesas | Altium acquired Upverter in 2017; Renesas completed its acquisition of Altium on August 1, 2024 (Renesas) |
| Mentor Graphics (PCB and IC design software, now Siemens EDA) | Siemens | Siemens completed the acquisition in March 2017 at an enterprise value of about $4.5 billion (Siemens) |
| DownStream Technologies (PCB manufacturing-data preparation) and ASTER Technologies (PCB assembly test engineering) | Siemens | Siemens acquired DownStream in April 2025 and ASTER in January 2026 (Siemens) |
| CadSoft EAGLE (PCB design software) | Autodesk | Autodesk acquired CadSoft from Premier Farnell in 2016 (Autodesk) |
| Simulation and analysis | ||
| Altair (mechanical and electromagnetic simulation, HPC and AI software) | Siemens | Siemens completed the acquisition on March 26, 2025, at an enterprise value of about $10 billion (Siemens) |
| Ansys (simulation and analysis software) | Synopsys | Synopsys completed the acquisition on July 17, 2025, originally valued at about $35 billion; PowerArtist was divested to Keysight in October 2025 (Synopsys; Keysight) |
| MSC Software (Hexagon’s Design & Engineering business, including MSC Nastran and Adams) | Cadence | Cadence completed the acquisition on February 23, 2026, for about €2.7 billion (Cadence) |
| Mechanical CAD and product lifecycle management | ||
| PTC (Creo and Onshape CAD, Windchill and Arena PLM) | PTC; Schneider Electric acquisition pending | Schneider Electric agreed on October 5, 2026, to acquire PTC for about $22.6 billion in equity value ($23.7 billion enterprise value); closing expected by Q3 2027, subject to approvals (PTC) |
Cadence describes Ultra Librarian’s models as CAD-agnostic while outlining deeper integration with its Allegro X and OrCAD X platforms (Cadence). Consolidation also extends beyond EDA vendors: semiconductor manufacturer Renesas acquired Altium in August 2024.
The channel that delivers a chipmaker’s CAD models now sits inside companies that also sell design tools.
When a chipmaker maintains its source assets in one CAD environment, serving other tools requires translation, export or additional model generation. Each step can introduce mapping errors, so every delivered format needs validation.
Tool diversity is structural. In an April 2026 Elektor reader poll, roughly two-thirds of respondents said they use KiCad, with paid tools at around 20% (Elektor). Enterprise teams mix Altium, Cadence, Siemens EDA and KiCad across groups and contractors. Owning one EDA tool covers one slice of that market.
The pattern repeats across the industry. Engineers post the same request on chipmaker community forums: an official, verified symbol and footprint for their tool.
Each request shows an engineer who stopped designing to find a footprint.
It is an early one. A CAD-model download shows that an engineer is evaluating a part. Depending on the delivery workflow and data agreements, the library provider, the manufacturer or a distributor may see that activity.
The industry says so openly. Supplyframe describes its platform as collecting continual data on design intent, demand, supply and risk (ChannelLife). In 2020, the SamacSys founder described the goal as helping suppliers use design-cycle intelligence to understand customer needs (Business Wire).
Three questions for every semiconductor company:
Design-in activity is one of the most valuable demand signals a chipmaker can observe. Know where it flows.
They add friction at the first step of a design, where long-term revenue starts. As TDK Micronas defines it, a design win usually holds for the life of the customer’s product (TDK Micronas). An engineer who stalls at the footprint may choose a part already in their library.
The cost to the customer is concrete. EMA Design Automation, now part of Cadence, estimates engineers spend 8 to 16 hours on average buildig one high-pin-count symbol and footprint by hand (EMA Design Automation). A footprint error can pass DRC and surface only at assembly, when the fix is a new board.
A Lifecycle Insights study cited by Electronic Design in 2019 found an average of 2.9 respins per project across all causes, with each respin taking 8.5 days and costing $44,000 on average (Electronic Design).
Library errors also travel with downloaded files. In one TI forum thread, a customer found that the KiCad model for a 0201 package was 0402-sized, and TI confirmed the file was wrong (TI E2E).
A launch pays off when the footprint is correct, in the customer’s tool, on day one.
It generates native CAD assets from the chipmaker’s own source documents, validates them, and delivers them for the tools customers use, independent of any EDA vendor. It has four properties.
Neurocad provides this layer. It sits between engineering documentation and the CAD tools engineers already use, and writes assets natively into each one, including Altium, Cadence and Siemens environments. IPC standards are built in as deterministic constraints on every part it generates.
For a chipmaker, a vendor-neutral layer extends launch investment into every customer’s toolchain and keeps the design-start signal closer to home.
Take your three most recent launches and answer five questions. Any gap marks a design-in at risk.
See your newest part generated from its datasheet into Altium, Cadence, Siemens EDA, KiCad and major MCAD tools.
ECAD models are the schematic symbols, PCB footprints and 3D models engineers use to place a component in a circuit board design. Each EDA tool, such as Altium, Cadence OrCAD or KiCad, stores them in its own format.
Many chipmakers link to third-party libraries such as SamacSys and Ultra Librarian. SamacSys is part of Siemens through Supplyframe. Ultra Librarian became part of Cadence through EMA Design Automation in 2026, and Cadence describes its models as CAD-agnostic.
They want a footprint verified against the manufacturer’s datasheet to avoid pin-numbering and land-pattern errors. Generic and converted footprints require manual checking.
A design-in is the integration of a component into a customer’s product design. A part that wins the design usually stays for that product’s lifetime.
A native model is written directly in the target tool’s format. A converted model is translated from another format, which can lose pad definitions, pin maps or 3D detail.
A vendor-neutral source generates assets for every major EDA and MCAD tool and operates independently of EDA vendors. Neurocad generates native assets from datasheets in Altium, Cadence, Siemens EDA, KiCad, SolidWorks, Fusion and Inventor.